Googlers say that AI can speed up chip design and perhaps keep Moore’s Law alive


We’ve seen plenty of hand wringing over the imminent demise of Moore’s Law. This is the observation made by Intel co-founder and ex-CEO Gordon Moore that in its current iteration calls for the number of transistors on a chip to double every two years. Using Apple’s A-series chipsets as an example, the A13 Bionic launched in 2019 powering the iPhone 11 series.

Will Artificial Intelligence (AI) be able to keep Moore’s Law alive after the 2nm node?

Built using the 7nm process node with just under 90 million transistors per square mm, the A13 Bionic contains 8.5 billion transistors. The A14 Bionic chipset is found in the iPhone 12 series and in the iPad Air (2020) and carries 134 million transistors per square mm. The chip’s transistor count is 11.8 billion; the more transistors inside a chip the more powerful and energy-efficient it is.

Next quarter the world’s top foundry, TSMC, is expected to test 4nm chips with mass production of the 3nm process node starting in the second half of next year. Both TSMC and Samsung are working on the 2nm process node which could be mass produced as soon as 2024. There are concerns about the future of Moore’s Law especially after the 2nm process node.

But there might be some help coming from Artificial Intelligence (AI). An article that discusses the use of AI in the process of creating a “floorplan” for a chip, notes that with AI, the time to build a floorplan, which can take as long as several months to finish, will be completed in less than 6-hours using AI. Chip floorplanning is the act of designing the lay out of a computer chip.

Google has already used AI to help design Tensor Processing Units

The Googlers who wrote about the technique for Nature are Azalia Mirhoseini and Anna Goldie. Google has used this system in real-life to help create the floorplan for its Tensor Processing Unit (TPU) which is used to “accelerate the neural networks in its search engine, public cloud, AlphaGo and AlphaZero, and other projects and products.” The article states that “In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area.”
Mirhoseini and Goldie wrote in their article that “Our method was used to design the next generation of Google’s artificial-intelligence accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields.”

The Neural Network gets better at designing the chips over time and “is “capable of generalizing across chips — meaning that it can learn from experience to become both better and faster at placing new chips — allowing chip designers to be assisted by artificial agents with more experience than any human could ever gain.” The paper concludes that “We show that our method can generate chip floorplans that are comparable or superior to human experts in under six hours, whereas humans take months to produce acceptable floorplans for modern accelerators. Our method has been used in production to design the next generation of Google TPU.”

The hope is that using AI to design upcoming chips will lead to solutions that will bring process nodes down to under 1nm. At the present time, as Mirhoseini and Goldie point out, “our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google’s artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation.”


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